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For many decades, ray tracing is known and well used for rendering highly realistic images. Since ray tracing simulates the physical transport of light even highly complex optical properties and illumination conditions can be rendered correctly. Due to these features ray tracing is used e.g. for commercials and movies, in architecture, and for visualizations of industrial prototypes. Especially for latter application it is of great advantage that ray tracing can handle highly complex models very well. However, achieving this high standard in image quality requires relatively complex calculations and a rather unstructured memory access behavior. For these reasons rendering an image of a simple scene already takes several minutes on standard processors, while complex simulations can run for many hours. Using high-end processors and multiprocessor machines does not solve the issue of rendering time in general and therefore will not be an option for realtime applications in the next years. Due to the same reasons – complex calculations and unstructured memory access patterns – previous attempts to built special hardware to accelerate full featured ray tracing for general applications did not provide the necessary processing power. This thesis presents how the ray tracing algorithm can be restructured to allow for structured memory accesses. Using these modifications a complete hardware architecture for realtime ray tracing is developed and verified using cycle-accurate simulations. Finally, these new techniques allowed for the world’s first prototype implementation of full featured ray tracing of complex environments on a single chip.